ソースコード表示テスト
ソースコード表示のテストです。
まずは、唐辛子というコンバーターを使った結果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity yccdatapath is
port (
yin : in std_logic_vector(7 downto 0);
cbin : in std_logic_vector(7 downto 0);
crin : in std_logic_vector(7 downto 0);
rout : out std_logic_vector(4 downto 0);
gout : out std_logic_vector(5 downto 0);
bout : out std_logic_vector(4 downto 0)
);
end;
architecture rtl of yccdatapath is
function stdv2str(vec:std_logic_vector) return string is
variable str : string(vec'length downto 1);
begin
for i in vec'length-1 downto 0 loop
if(vec(i)='U') then
str(i+1) := 'U';
elsif(vec(i)='X') then
str(i+1) := 'X';
elsif(vec(i)='0') then
str(i+1) := '0';
elsif(vec(i)='1') then
str(i+1) := '1';
elsif(vec(i)='Z') then
str(i+1) := 'Z';
elsif(vec(i)='W') then
str(i+1) := 'W';
elsif(vec(i)='L') then
str(i+1) := 'L';
elsif(vec(i)='H') then
str(i+1) := 'H';
else
str(i+1) := '-';
end if;
end loop;
return str;
end;
function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length + b'length -1 downto 0);
begin
z := std_logic_vector(signed(a) * signed(b));
-
- report "a=" & stdv2str(a) severity NOTE;
- report "a integer =" & integer'image(TO_INTEGER(signed(a))) severity NOTE;
- report "b=" & stdv2str(b) severity NOTE;
- report "b integer =" & integer'image(TO_INTEGER(signed(b))) severity NOTE;
- report "a*b integer =" & integer'image(TO_INTEGER(signed(a))* TO_INTEGER(signed(b))) severity NOTE;
-- report "a*b=" & stdv2str(z) severity NOTE;
return(z);
end;
function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
variable ex_a : std_logic_vector(a'length downto 0);
variable ex_b : std_logic_vector(b'length downto 0);
variable z1 : std_logic_vector(a'length downto 0);
variable z2 : std_logic_vector(b'length downto 0);
begin
ex_a := a(a'left) & a;
ex_b := b(b'left) & b;
if( a'length > b'length)then
z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
return(z1);
else
z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
return(z2);
end if;
end;
signal node1 : std_logic_vector(9 downto 0);
signal node2 : std_logic_vector(9 downto 0);
signal node3 : std_logic_vector(15 downto 0);
signal node4 : std_logic_vector(15 downto 0);
signal node5 : std_logic_vector(15 downto 0);
signal node6 : std_logic_vector(15 downto 0);
signal node7 : std_logic_vector(9 downto 0);
signal node8 : std_logic_vector(8 downto 0);
signal node9 : std_logic_vector(9 downto 0);
signal node10 : std_logic_vector(9 downto 0);
begin
comb : process (yin, cbin, crin,node1,node2,node3,node4,node5,
node6,node7,node8,node9,node10)
begin
node1 <= mysigned_add
node2 <= mysigned_add(('0' & crin), "110000000");
node3 <= mysigned_mul("01011010", node2(7 downto 0">*1;
node4 <= mysigned_mul("11101010", node1(7 downto 0));
node5 <= mysigned_mul("11010010", node2(7 downto 0));
node6 <= mysigned_mul("01110001", node1(7 downto 0));
node7 <= mysigned_add*2;
node8 <= mysigned_add*3;
node9 <= mysigned_add*4;
node10 <= mysigned_add(('0' & yin), node8);
if(node7(9) = '1') then
rout <= "00000";
elsif(node7(8) = '1') then
rout <= "11111";
else
rout <= node7(7 downto 3);
end if;
if(node10(9) = '1') then
gout <= "000000";
elsif(node10(8) = '1') then
gout <= "111111";
else
gout <= node10(7 downto 2);
end if;
if(node9(9) = '1') then
bout <= "00000";
elsif(node9(8) = '1') then
bout <= "11111";
else
bout <= node9(7 downto 3);
end if;
end process;
end;
次にSourceConverterというソフトを使った結果。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity yccdatapath is
port (
yin : in std_logic_vector(7 downto 0);
cbin : in std_logic_vector(7 downto 0);
crin : in std_logic_vector(7 downto 0);
rout : out std_logic_vector(4 downto 0);
gout : out std_logic_vector(5 downto 0);
bout : out std_logic_vector(4 downto 0)
);
end;
architecture rtl of yccdatapath is
function stdv2str(vec:std_logic_vector) return string is
variable str : string(vec'length downto 1);
begin
for i in vec'length-1 downto 0 loop
if(vec(i)='U') then
str(i+1) := 'U';
elsif(vec(i)='X') then
str(i+1) := 'X';
elsif(vec(i)='0') then
str(i+1) := '0';
elsif(vec(i)='1') then
str(i+1) := '1';
elsif(vec(i)='Z') then
str(i+1) := 'Z';
elsif(vec(i)='W') then
str(i+1) := 'W';
elsif(vec(i)='L') then
str(i+1) := 'L';
elsif(vec(i)='H') then
str(i+1) := 'H';
else
str(i+1) := '-';
end if;
end loop;
return str;
end;
function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length + b'length -1 downto 0);
begin
z := std_logic_vector(signed(a) * signed(b));
-
- report "a=" & stdv2str(a) severity NOTE;
- report "a integer =" & integer'image(TO_INTEGER(signed(a))) severity NOTE;
- report "b=" & stdv2str(b) severity NOTE;
- report "b integer =" & integer'image(TO_INTEGER(signed(b))) severity NOTE;
- report "a*b integer =" & integer'image(TO_INTEGER(signed(a))* TO_INTEGER(signed(b))) severity NOTE;
- report "a=" & stdv2str(a) severity NOTE;
-- report "a*b=" & stdv2str(z) severity NOTE;
return(z);
end;
function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
variable ex_a : std_logic_vector(a'length downto 0);
variable ex_b : std_logic_vector(b'length downto 0);
variable z1 : std_logic_vector(a'length downto 0);
variable z2 : std_logic_vector(b'length downto 0);
begin
ex_a := a(a'left) & a;
ex_b := b(b'left) & b;
if( a'length > b'length)then
z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
return(z1);
else
z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
return(z2);
end if;
end;
signal node1 : std_logic_vector(9 downto 0);
signal node2 : std_logic_vector(9 downto 0);
signal node3 : std_logic_vector(15 downto 0);
signal node4 : std_logic_vector(15 downto 0);
signal node5 : std_logic_vector(15 downto 0);
signal node6 : std_logic_vector(15 downto 0);
signal node7 : std_logic_vector(9 downto 0);
signal node8 : std_logic_vector(8 downto 0);
signal node9 : std_logic_vector(9 downto 0);
signal node10 : std_logic_vector(9 downto 0);
begin
comb : process (yin, cbin, crin,node1,node2,node3,node4,node5,
node6,node7,node8,node9,node10)
begin
node1 <= mysigned_add
node2 <= mysigned_add(('0' & crin), "110000000");
node3 <= mysigned_mul("01011010", node2(7 downto 0">*5;
node4 <= mysigned_mul("11101010", node1(7 downto 0));
node5 <= mysigned_mul("11010010", node2(7 downto 0));
node6 <= mysigned_mul("01110001", node1(7 downto 0));
node7 <= mysigned_add*6;
node8 <= mysigned_add*7;
node9 <= mysigned_add*8;
node10 <= mysigned_add(('0' & yin), node8);
if(node7(9) = '1') then
rout <= "00000";
elsif(node7(8) = '1') then
rout <= "11111";
else
rout <= node7(7 downto 3);
end if;
if(node10(9) = '1') then
gout <= "000000";
elsif(node10(8) = '1') then
gout <= "111111";
else
gout <= node10(7 downto 2);
end if;
if(node9(9) = '1') then
bout <= "00000";
elsif(node9(8) = '1') then
bout <= "11111";
else
bout <= node9(7 downto 3);
end if;
end process;
end;
うーん、、、、どっちも好みではないなー。
調整できるのかもしれないけど。
後記
marseeさんから、SourceConverterを使った後に
を消して使っているとアドバイスがあったのでやってみました。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity yccdatapath is
port (
yin : in std_logic_vector(7 downto 0);
cbin : in std_logic_vector(7 downto 0);
crin : in std_logic_vector(7 downto 0);
rout : out std_logic_vector(4 downto 0);
gout : out std_logic_vector(5 downto 0);
bout : out std_logic_vector(4 downto 0)
);
end;
architecture rtl of yccdatapath is
function stdv2str(vec:std_logic_vector) return string is
variable str : string(vec'length downto 1);
begin
for i in vec'length-1 downto 0 loop
if(vec(i)='U') then
str(i+1) := 'U';
elsif(vec(i)='X') then
str(i+1) := 'X';
elsif(vec(i)='0') then
str(i+1) := '0';
elsif(vec(i)='1') then
str(i+1) := '1';
elsif(vec(i)='Z') then
str(i+1) := 'Z';
elsif(vec(i)='W') then
str(i+1) := 'W';
elsif(vec(i)='L') then
str(i+1) := 'L';
elsif(vec(i)='H') then
str(i+1) := 'H';
else
str(i+1) := '-';
end if;
end loop;
return str;
end;
function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
variable z : std_logic_vector(a'length + b'length -1 downto 0);
begin
z := std_logic_vector(signed(a) * signed(b));
-
- report "a=" & stdv2str(a) severity NOTE;
- report "a integer =" & integer'image(TO_INTEGER(signed(a))) severity NOTE;
- report "b=" & stdv2str(b) severity NOTE;
- report "b integer =" & integer'image(TO_INTEGER(signed(b))) severity NOTE;
- report "a*b integer =" & integer'image(TO_INTEGER(signed(a))* TO_INTEGER(signed(b))) severity NOTE;
-- report "a*b=" & stdv2str(z) severity NOTE;
return(z);
end;
function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
variable ex_a : std_logic_vector(a'length downto 0);
variable ex_b : std_logic_vector(b'length downto 0);
variable z1 : std_logic_vector(a'length downto 0);
variable z2 : std_logic_vector(b'length downto 0);
begin
ex_a := a(a'left) & a;
ex_b := b(b'left) & b;
if( a'length > b'length)then
z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
return(z1);
else
z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
return(z2);
end if;
end;
signal node1 : std_logic_vector(9 downto 0);
signal node2 : std_logic_vector(9 downto 0);
signal node3 : std_logic_vector(15 downto 0);
signal node4 : std_logic_vector(15 downto 0);
signal node5 : std_logic_vector(15 downto 0);
signal node6 : std_logic_vector(15 downto 0);
signal node7 : std_logic_vector(9 downto 0);
signal node8 : std_logic_vector(8 downto 0);
signal node9 : std_logic_vector(9 downto 0);
signal node10 : std_logic_vector(9 downto 0);
begin
comb : process (yin, cbin, crin,node1,node2,node3,node4,node5,
node6,node7,node8,node9,node10)
begin
node1 <= mysigned_add
node2 <= mysigned_add(('0' & crin), "110000000");
node3 <= mysigned_mul("01011010", node2(7 downto 0">*9;
node4 <= mysigned_mul("11101010", node1(7 downto 0));
node5 <= mysigned_mul("11010010", node2(7 downto 0));
node6 <= mysigned_mul("01110001", node1(7 downto 0));
node7 <= mysigned_add*10;
node8 <= mysigned_add*11;
node9 <= mysigned_add*12;
node10 <= mysigned_add(('0' & yin), node8);
if(node7(9) = '1') then
rout <= "00000";
elsif(node7(8) = '1') then
rout <= "11111";
else
rout <= node7(7 downto 3);
end if;
if(node10(9) = '1') then
gout <= "000000";
elsif(node10(8) = '1') then
gout <= "111111";
else
gout <= node10(7 downto 2);
end if;
if(node9(9) = '1') then
bout <= "00000";
elsif(node9(8) = '1') then
bout <= "11111";
else
bout <= node9(7 downto 3);
end if;
end process;
end;
これまでの二つよりは、かなり見やすくなりました。
*1:'0' & cbin), "110000000"); node2 <= mysigned_add(('0' & crin), "110000000"); node3 <= mysigned_mul("01011010", node2(7 downto 0
*2:'0' & yin), (node3(14 downto 7) & '0'
*3:node4(13 downto 7) & '0'), (node5(13 downto 7) & '0'
*4:'0' & yin), ( node6(14 downto 7) & '0'
*5:'0' & cbin), "110000000");
node2 <= mysigned_add(('0' & crin), "110000000");
node3 <= mysigned_mul("01011010", node2(7 downto 0
*6:'0' & yin), (node3(14 downto 7) & '0'
*7:node4(13 downto 7) & '0'), (node5(13 downto 7) & '0'
*8:'0' & yin), ( node6(14 downto 7) & '0'
*9:'0' & cbin), "110000000"); node2 <= mysigned_add(('0' & crin), "110000000"); node3 <= mysigned_mul("01011010", node2(7 downto 0
*10:'0' & yin), (node3(14 downto 7) & '0'
*11:node4(13 downto 7) & '0'), (node5(13 downto 7) & '0'
*12:'0' & yin), ( node6(14 downto 7) & '0'